Power management has become and will continue to be an important factor in computer system component design. One technique to reduce power consumption is to turn off input and/or output buffer circuits when an interconnect is idle for a period of time.
One interconnect implementation that is gaining industry acceptance is based on the PCI Express specification (PCI Express Base Specification, revision 1.0a). The PCI Express specification defines an active power management state called “L0s.” In this state, a device turns off its transmitters to save power whenever the transmitter is idle for up to 7 us.
A transmitting device on one side of a PCI Express point-to-point link is required to communicate to the receiving device on the other side of the link that the transmitting device is entering the L0s state. This is accomplished by delivering a packet of information called an “electrical idle ordered set” to the receiving device. In response to receiving the electrical idle ordered set, the receiving device enters the L0s state and turns off its receiver circuit (including input buffers). When the transmitting device exits the L0s state and desires to recommence communication with the receiving device, the transmitting device begins by delivering a series of “fast training sets” (FTS). An FTS includes special characters that are recognized by the receiving device and allow the receiving device to achieve bit and symbol synchronization following the period of no activity on the interconnect. A typical FTS is 4 bytes in length. The FTS series is received at the receiving device input circuitry, and after bit and symbol synchronization are achieved the FTS moves through the receiver pipeline circuitry until it is received by a power management unit that responds to the FTS by causing the receiving device to exit the L0s state. A typical PCI Express device may have a pipeline delay of 20 or so symbol clock periods.
The number of FTS that must be transmitted by the transmitting device to the receiving device depends on the greatest length of time it may require for the receiving device to recognize activity on the interconnect, turn on the receiver circuit, achieve bit and symbol lock, and reset receiver pipeline logic. When the transmitting device and the receiving device first detect each other's presence, perhaps at system start-up, the receiving device must communicate to the transmitting device the minimum number of FTS that must be transmitted by the transmitting device to the receiving device when exiting the L0s state.
A problem may occur when the transmitting device enters L0s (sending an electrical idle ordered set to the receiving device) and quickly (in as little as 20 ns) exits L0s (thereby beginning transmission of the FTS series). In this case, the transmitting device would exit L0s and start transmitting FTS before the electrical idle ordered set has a chance to move through the receiving device pipeline and be recognized by the power management unit. In this situation, the power management unit will cause the receiving device to enter the L0s state (turning off the receiver circuitry) even though the transmitting device is already sending FTS. The receiving device will exit L0s soon thereafter in response to the continued activity on the interconnect, but a number of FTS will have gone by without being recognized by the receiving device. Thus, the transmitting device may begin to send higher-level packets before the receiving device is prepared to receive the packets, and the data will be lost.
To counter this difficulty, the minimum number of FTS that must be transmitted from the transmitting device to the receiving device when the transmitting device exits the L0s state is inflated to cover the pipeline delay time, thereby ensuring that the receiving device will receive adequate time to enter and exit the L0s state and be prepared to receive higher-level packet data even in the case where the transmitting device enters and exits L0s quickly.
Low power states such as L0s are most useful when they can be entered and exited as quickly as possible. Low entry and exit latencies allow the low power states to be applied more liberally without adversely affecting interconnect performance.